The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, it relates to a semiconductor device equipped with an SRAM and a method for fabricating the same.
Refinement of semiconductor devices equipped with SRAMs has been conventionally accelerated to meet demands for large capacity and a high degree of integration. Owing to the structure of an SRAM, it is necessary to dispose substrate contact regions at a given interval in a memory cell array for obtaining potential of a drain region of a driver transistor. Therefore, it is necessary to consider not only a memory cell but also a substrate contact region in examination for refinement.
In a conventional semiconductor device equipped with a general SRAM, a substrate contact region is separated from an adjacent N-type MIS transistor by an isolation region (see, for example, Japanese Laid-Open Patent Publication No. 2004-39902).
Now, a conventional semiconductor device equipped with an SRAM and a method for fabricating the same will be described with reference to FIGS. 8A, 8B and 9A through 9E. FIG. 8A is a plan view for showing the structure of the conventional semiconductor device equipped with an SRAM and FIG. 8B is a cross-sectional view thereof taken on line C-C of FIG. 8A. As shown in FIGS. 8A and 8B, an active region 200a of a first driver transistor TrD1, an active region 200b of a second driver transistor TrD2, an active region 200c of a first access transistor TrA1, an active region 200d of a second access transistor TrA2 and a substrate contact region 200e are separated from one another by isolation insulating films 206a and 206b in the conventional semiconductor device.
Gate electrodes 209a, 209b, 209c and 209d are respectively formed on the active regions 200a, 200b, 200c and 200d of the transistors TrD1, TrD2, TrA1 and TrA2. Also, contact plugs 215a through 215h are formed on both sides of the gate electrodes 209a through 209d in the active regions 200a through 200d. The contact plugs 215a through 215h are respectively connected to metal lines 217a through 217h. 
Next, the method for fabricating the conventional semiconductor device equipped with an SRAM will be described with reference to FIGS. 9A through 9E. FIGS. 9A through 9E are cross-sectional views for showing procedures in fabrication of the conventional semiconductor device equipped with an SRAM. In FIGS. 9A through 9E, the cross-section taken on line C-C of FIG. 8A is shown.
In the fabrication method for the conventional semiconductor device, a silicon oxide film 201 and a silicon nitride film 202 are first formed on a semiconductor substrate 200 by a known film forming technique in the procedure shown in FIG. 9A.
Next, in the procedure shown in FIG. 9B, a resist (not shown) having an opening in an isolation forming region is formed on the silicon nitride film 202, and the silicon nitride film 202 is etched by using the resist as a mask, so as to form a patterned silicon nitride film 202a. Thereafter, the silicon oxide film 201 is etched into a silicon oxide film 201a by using the resist or the silicon nitride film 202a as a mask, and then, the semiconductor substrate 200 is dry etched so as to form trenches 205a and 205b. The trench 205a is disposed between an active region 203a of an N-type driver transistor of an N-type MIS transistor and a substrate contact region 204, and the trench 205b is disposed between an active region 203b of an N-type access transistor of an N-type MIS transistor and the substrate contact region 204.
Next, in the procedure shown in FIG. 9C, a silicon oxide film 206 is formed over the semiconductor substrate 200 including the inside of the trenches 205a and 205b by plasma CVD using HDP (high density plasma).
Then, in the procedure shown in FIG. 9D, the silicon oxide film 206 is polished and removed by CMP until the surface of the silicon nitride film 202a is exposed, and thus, isolation insulating films 206a and 206b made of the silicon oxide film are formed in the trenches 205a and 205b. 
Subsequently, in the procedure shown in FIG. 9E, the silicon nitride film 202a and the silicon oxide film 201a are removed, and thus, an isolation region made of the isolation insulating films 206a and 205b filled in the trenches 205a and 205b is formed.
Thereafter, a P-type well region 207, a P-type impurity region 218, gate insulating films 208a and 208b, gate electrodes 209a, 209b and 209c, a sidewall 210, N-type source/drain regions 211a and 211b, a metal silicide film 212, a liner film 213, an interlayer insulating film 214, contact plugs 215a through 215j, an interlayer insulating film 216 and metal lines 217a through 217h shown in FIG. 8 are formed by employing known techniques.
In this manner, a semiconductor device equipped with an SRAM including access transistors and driver transistors is fabricated.
The conventional semiconductor device equipped with an SRAM has, however, the following problems:
In the case where the isolation region is formed in the semiconductor substrate 200 by filling the trenches 205a and 205b with the isolation insulating films 206a and 206b by the method shown in FIGS. 9A through 9E, there arises a problem that large stress is applied by the isolation region to the active region 200a of the first driver transistor, the active region 200b of the second driver transistor, the active region 200c of the first access transistor and the active regions 200d of the second access transistor shown in FIGS. 8A and 8B. This is because stress derived from a difference in the thermal expansion coefficient between silicon and a silicon oxide film and from oxidation of a silicon substrate is caused around the isolation region in the procedure for filling the trenches with the silicon oxide films and annealing procedure for oxidation/activation annealing or the like.
The stress is increased as the width of the trench is reduced for the refinement, and the stress not only degrades the performances of the transistors but also may cause crystal defects or dislocation, leakage of a diffusion layer or a well, or a short-circuit between elements. As a result, the semiconductor device equipped with an SRAM has problems that the increase of the degree of integration is inhibited, that the improvement of the performance is suppressed and that the power consumption is increased.